1. Field of Invention
This invention relates to testing of semiconductor integrated circuits and in particular testing of parameter degradation caused by hot carrier injection.
2. Description of Related Art
Conventional methods of testing for hot carrier effects on semiconductor transistor parameters are limited by the drain to source punch-through voltage. The effect on transistor parameters is a degradation over time, and the testing is required to assure the parameters meet a certain criteria throughout the specified life of the product. As semiconductor devices are scaled to be smaller for density and performance reasons, punch-through can be more restrictive forcing a lower stress voltage and requiring longer testing time.
In U.S. Pat. No. 5,598,009 (Bui) is described a CMOS transistor design for optimal hot carrier testing. In this scheme is a transistor designed to have multiple common gate areas. There is an adjustment of the pad area to the gate area to minimize deleterious plasma currents. In U.S. Pat. No. 5,587,665 (Jiang) is disclosed a special test circuit for determining performance degradation resulting from hot carrier stress. The test circuit is formed by a string of inverters connected in series. Every other inverter in the series connection is designed to not be sensitive to hot carriers. Thus a signal transition delay is amplified by every other inverter that is sensitive to hot carrier effects on delay. In reference to "ULSI Technology" edited by C. Y Chang and S. M. Sze, McGraw Hill 1996, pp 657-662 is described the reliability effect of hot carrier injection. The fundamental mechanism and equations of the hot carrier effects are described.
In the conventional method of testing reliability of a semiconductor product for hot carrier effects, a drain to source stress voltage is applied for a period of time and parameters are measured for degradation. The time that is required by the test samples under test can be of considerable length. This time can be reduced by increasing the drain to source stress voltage. The magnitude of the stress voltage is limited by the source to drain punch-through of the transistors under test, and limits the reduction in test time for obtaining a reasonable lifetime prediction of the hot carrier effect.